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fast, complete 12-bit a/d converters ad adc84/ad adc85 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features performance complete 12-bit a/d converter with reference and clock fast successive approximation conversion: 10 s or 5 s buried zener reference for long-term stability and low gain tc: 10 ppm/c max nonlinearity: < 0.012% low power: 880 mw typ low chip counthigh reliability industry-standard pinout z models for 12 v operation available mil-std-883b processing available versatility negative true parallel logic outputs short cycle capability precision +6.3 v reference for external applications product description the ad adc84/ad adc85 series devices are high speed, low cost 12-bit successive approximation analog-to-digital converters that include an internal clock, reference, and comparator. its hybrid ic design utilizes msi digital and linear monolithic chips in conjunction with a 12-bit monolithic dac to provide modular performance and versatility with ic size, price, and reliability. important performance characteristics of the ad adc84/ ad adc85 series include maximum linearity error of 0.012%; gain tc below 15 ppm/c at 25c; typical power dissipation of 880 mw; and conversion time of less than 10 s for the 12-bit versions. of considerable significance in severe and aerospace applications is the guaranteed performance from C55c to +125c of the ad adc85s, which is also available with environmental screening. monotonic operation of the feedback dac guarantees no missing codes over temperature ranges of 0c to +70c, C25c to +85c, and C55c to +125c. the design of the ad adc84/ad adc85 includes scaling resistors that provide analog input signal ranges of 2.5 v, 5 v, 10 v, 0 v to +5 v, or 0 v to +10 v. the 6.3 v precision reference, which can be used for external applications, and the input buffer amplifier add flexibility and value. all digital signals are fully dtl and ttl compatible, and the data output is negative-true and available in parallel form. the ad adc84/ad adc85 are available in a performance grade specified for 12-bit accuracy (0.012% fsr max) with 10 s maximum conversion time. figure 1. functional block diagram the ad adc84 and ad adc85c are specified for operation over the 0c to +70c temperature range. the ad adc85 and ad adc85s are specified for the C25c to +85c and C55c to +125c ranges, respectively. the serial output function is no longer supported on the ad adc84/ad adc85 after date code 9623. product highlights 1. the ad adc84/ ad adc85 series devices are complete 12-bit adcs. no external components are required to perform a conversion. 2. the ad adc84/ ad adc85 directly replaces other devices of this type with significant increases in performance. 3. the fast conversion rates of the ad adc84 and ad adc85 (10 s) make them an excellent choice for applications requiring high system throughput rates. 4. the internal buried zener reference is laser trimmed to 6.3 v 0.1% and 10 ppm/c typical tc. the reference is available externally and can provide up to 1 ma. 5. the integrated package construction provides high quality and reliability with small size and weight. 6. the monolithic 12-bit feedback dac is used for reduced chip count and higher reliability. 7. the ad adc85s/883b comes processed to mil-std-883, class b requirements.
ad adc84/ad adc85 rev. b | page 2 of 12 table of contents specifications..................................................................................... 3 typical performance characteristics ............................................. 5 functional description .................................................................... 6 offset adjustment ........................................................................ 6 gain adjustment........................................................................... 6 theory of operation .................................................................... 6 timing............................................................................................ 6 digital output data ..................................................................... 7 input scaling ..................................................................................8 input voltage range and lsb values ..........................................8 calibration......................................................................................9 grounding ......................................................................................9 clock rate control alternate connections............................ 10 microprocessor interfacing....................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history revision b 11/03data sheet changed from rev. a to rev. b removed ad5240...............................................................universal updated format ...................................................................universal added text to product description .................................. 1 updated outline dimensions ............................................ 11
ad adc84/ad adc85 rev. b | page 3 of 12 specifications table 1. typical @ 25c, 15 v and +5 v, unless otherwise noted model ad adc84 ad adc85c ad adc85 ad adc85s unit resolution 12 12 12 12 bits analog inputs voltage ranges bipolar 2.5, 5, 10 * * * v unipolar 0 to +5, 0 to +10 * * * v impedance (direct input) 0 v to +5 v, 2.5 v 2.5 (20%) * * * k? 0 v to +10 v, 5 v 5 (20%) * * * k? 10 v 10 (20%) * * * k? buffer amplifier 1 impedance (min) 100 * * * m? bias current 50 * * * na settling time to 0.01% for 20 v step 2 * * * s digital inputs 2 convert command positive pulse 100 ns min trailing edge initiates conversion * * * logic loading 1 * * * ttl load transfer characteristics error gain error 3 0.1 (0.25% max) * * * % offset error 3 adjustable to zero * * * unipolar 0.05 (0.2% max) * * * % of fsr 4 bipolar 5 0.1 (0.25% max) * * * % of fsr linearity error (max) 6 0.012 * * * % of fsr inherent quantization error 0.5 * * * lsb differential linearity error 0.5 * * * lsb no missing codes temperature range 0 to +70 0 to +70 C25 to +85 C55 to +125 c power supply sensitivity 15 v 0.004 * * * % of fsr/% v +5 v 0.001 * * * % of fsr/% v drift specification temperature range 0 to +70 * C25 to +85 C55 to +125 c gain (max) 30 25 15 25 ppm/c offset unipolar 3 * * 5 max ppm/c bipolar (max) 5 15 12 7 10 ppm/c linearity 3 * 2 * ppm/c monotonicity guaranteed * * * conversion speed (max) 10 * * * s
ad adc84/ad adc85 rev. b | page 4 of 12 model ad adc84 ad adc85c ad adc85 ad adc85s unit digital output (all codes complementary) parallel output codes 7 unipolar csb * * * bipolar cob, ctc * * * output drive 2 * * * ttl loads status logic 1 during conversion * * * status output drive 2 * * * ttl loads internal clock clock output drive 2 * * * ttl loads frequency 1.9/1.22 * * * mhz internal reference voltage 6.3/15 mv max * * * v maximum external current (with no degradation of specifications) 1.0 * * * ma tempco of drift (max) 20 max 10 typ 5 typ 5 typ ppm/c power requirements rated voltages +5, 15 * * * v range for rated accuracy +4.75 to +5.25 and 13.5 to C16.5 * * * v z models 8 +4.75 to +5.25 and 11.4 to C16.5 * * * v supply drain +15 v 25 max * * * ma C15 v 35 max * * * ma +5 v 140 max * * * ma total power dissipation 1500 max * * * mw temperature range specification 0 to +70 * C 25 to +85 C55 to +125 c operating (derated specs) C25 to +85 * C55 to +125 C55 to +125 c storage C55 to +125 * * * c package option 9 dh-32f ceramic ceramic ceramic ceramic *specifications same as ad adc84. 1 buffer settling time adds to conversion speed when buffer is connected to input. 2 dtl/ttl compatible logic 0 = 0.8 v max, logic 1 = 2.0 v min for digital output, logic 0 = 0.4 v max, logic 1 = 2.4 v min. 3 adjustable to zero. 4 fsr means full-scale range. 5 guaranteed at vin = 0 v. 6 error shown is the same as 1/2 lsb max error in % of fsr. 7 see table 2. 8 for 12 v operation, add z to model numbe r. input range limited to a maximum of 5 v. 9 for package outline information, see outline dimens ions section.
ad adc84/ad adc85 r e v. b | pa ge 5 o f 1 2 typical perf orm ance cha r acte ristics f i gure 2. li ne ar it y e r r o r v s . con v e r s i o n speed f i g u re 3. g a in d r if t e r r o r ( % fsr ) v s . t e mpe r at u r e f i gur e 4 . cha n ge i n di ffe r e ntia l li ne ar it y vs . c o n v e r sio n sp e e d f i gure 5. con v ers i o n speed v s . control v o lt age
ad adc84/ad adc85 r e v. b | pa ge 6 o f 1 2 functional description offset adjustment th e z e ro a d j u st c i rc u i t c o ns i s t s of a p o te n t i o me te r c o n n e c te d acr o ss v s wi th i t s s l i d e r co nn e c t e d th r o ugh a 1. 8 m r e si s t o r t o c o m p a r a t o r i n p u t p i n 22 f o r al l ra n g es. a s sh o w n in f i gur e 6, t h e t o leran c e o f t h is f i xe d r e sist o r is n o t cr i t ic a l , a nd a ca r b o n co m p osi t ion ty p e is ge n e ra l l y ade q u a te . u s i n g a ca r b o n co m p osi t ion r e sis t o r ha vin g a C1200 p p m /c t e m p co con t r i b- u t es a w o rs t-c a s e o f fs et t e m p co o f 8 244 10 C6 1200 p p m /c = 2.3 p p m / c o f fs r , if t h e offs et a d j p o t e n t io m e t e r is s e t a t ei t h er end o f i t s ad j u s t m e n t ra ng e . sin c e t h e maxim u m o f fs et ad j u s t m e n t r e q u ir ed is typ i cal l y n o m o r e than 4 ls b , us e o f a ca rbon com p osi t io n o f fs et s u mmin g r e sis t o r ty p i cal l y co n t r i b u t e s n o m o r e than 1 p p m/c o f fs r o f f s et t e m p co . f i gure 6 . o ffset a d justm e nt cir c ui t an al t e r n a t e o f fs et ad j u st cir c ui t, w h ich co n t r i b u t e s neg l ig i b le o f fs et t e m p co if m e t a l f i lm r e sis t o r s (t em p c o <1 00 p p m / c) a r e us ed , is sh o w n in f i gur e 7. f i gure 7. l o w t e mpc o ze r o adjustm e n t circuit i n e i t h e r z e ro a d j u st c i rc u i t , t h e f i x e d re s i stor c o n n e c te d to pi n 22 s h o u ld b e lo ca te d clos e t o t h is p i n t o k e ep t h e p i n conn e c t i on r u ns shor t . ( c om p a r a tor in put pi n 2 2 i s qu ite s e ns it iv e to ext e r n al n o is e pick u p ). gain adjus t ment th e g a i n a d j u s t c i rc u i t c o ns i s t s of a p o te n t i o me te r c o n n e c te d acr o ss v s wi th i t s s l i d e r co nn e c t e d th r o ugh a 10m r e si s t o r t o th e g a in a d j u s t p i n 27 as sh o w n in f i gur e 8. f i gure 8. g a i n adju stment ci r c u i t an a l t e r n a t e ga i n ad j u st cir c ui t w h ich co n t r i b u tes n e g l ig ib le ga in t e m p co if m e t a l f i lm r e sis t o r s (t em p c o < 100 p p m /c) a r e us ed is sh o w n in f i gur e 9. f i g u re 9. l o w t e mpc o g a in adjus t men t circuit 8 4 / h e e r i o d , d e p e n d i ng o n t h e c o m p a r at o r at t h at t i m e . a ta a li d o n th e sa m e ta e r t o be in i t ia t e d b y th e tra i lin g d g e o f th e s t a t u s s i gn al . theory of operat ion on r e cei p t o f a c o nver t st ar t command , t h e ad ad c ad a d c85 con v er ts t h e v o l t a g e as i t s a n alog i n p u t i n t o an e q u i v a l e n t 1 2 - bi t bi n a r y n u m b e r . t h i s c o n v e r s i on i s acco m p lish e d as f o l l o w s: th e 1 2 -b i t s u cces s i v e a p p r o x ima t i o n r e g i s t er (sar) has i t s 12 -b i t o u t p u t s co nn e c t e d bo th t o th e de vice b i t o u t p ut p i n s and t o t h e co r r esp o n d ing b i t in p u ts o f t h e f eed ba ck d a c . t h e a n al og i n p u t i s s u cce s s i v e l y co m p a r ed t o t f e e d b a c k d a c output , on e bit at a t i me ( m sb f i r s t , l s b l a s t ) . the decision t o k e ep o r r e jec t e a c h b i t is t h en made a t t h e c o m p l e t i on of e a ch bit c o m p ar i s on p s t a t e o f t h e timi ng the timin g dia g ra m is sh o w n in f i gur e 10. recei p t o f a c o nver t st ar t sig n a l s e ts t h e st a t us f l ag, indic a t i n g co n v ersio n in pr og r e ss. this, in t u r n , r e m o v e s t h e i n h i b i t a p pl i e d to t h e g a te d cl o c k , p e r m it t i ng i t to r u n t h rou g h 1 3 c y cles. a l l t h e sar p a ral l e l b i ts, st a t us f l i p -f lo ps, a n d t h e ga t e d clo c k i n hib i t sig n a l a r e in i t ia li ze d o n t h e t r a i lin g e d ge o f t h e c o nver t st ar t sig n a l . a t t i m e t 0 , bi t 1 is r e s e t a nd bi t 2 t o b i t 12 a r e s e t un con d i t io nal l y . a t t 1 , th e bi t 1 deci si o n i s m a de (k e e p) and bi t 2 is un con d i t io n a l l y r e s e t. a t t 2 , t h e b i t 2 d e c i s i o n is made ( k e e p) a nd bi t 3 is r e s e t un condi t i o n a l ly . this s e q u e n c e co n t in ues un til th e b i t 12 (ls b ) decisio n ( k eep) is made a t t 12 . af t e r a 40 n s dela y p e r i o d , t h e s t a t us f l a g is r e s e t, in dica t i n g th a t t h e co n v e r si o n i s co m p let e a n d th a t th e pa ralle l o u t p u t d is valid . re s e t t ing t h e st a t us f l a g r e s t o r es t h e ga t e d clo c k i n hi b i t si gn al , f o r c i n g th e c l ock o u t p u t t o th e logi c 0 s t a t e . c o rr e s po n d in g pa ralle l da ta b i ts beco m e v pos i ti v e - g o i n g cl oc k ed g e (s ee f i gur e 10). i n co r p o r a t i o n o f th e 40n s de la y gua r a n t e e s th a t th e pa r a l l e l da is valid a t t h e l o g i c 1 t o 0 tra n si tio n o f t h e s t a t us f l a g , pe rm i t ti n g pa ra lle l da ta tra n sf e
ad adc84/ad adc85 rev. b | page 7 of 12 notes 1. the convert start pulse width is 100ns min and must remain low during a conv ersion. the conversion is initiated by the trailing edge of the convert command. 2. 10s for 12 bits (ad adc84/ad adc85). 3. msb decision. 4. lsb decision 20ns prior to the status going low. *bit decisions. figure 10. timing diagram (binary code 011001110110) digital output data parallel data from ttl storage registers are in negative true form. parallel data coding is complementary binary for unipolar ranges and either complementary offset binary or complementary twos complement binary, depending on whether bit 1 (pin 12) or its logical inverse bit 1 (pin 13) is used as the msb. parallel data becomes valid approximately 40 ns before the status flag returns to logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the status flag. parallel data outputs change state on positive-going clock edges. there are 13 negative-going clock edges in the complete 12-bit conversion cycle, as shown in figure 10. the first edge shifts an invalid bit into the register, which is shifted out on the 13th negative-going clock edge. short cycle input a short cycle input, pin 14, permits the timing cycle shown in figure 10 to be terminated after any number of desired bits has been converted, permitting somewhat shorter conversion times in applications not requiring full 12-bit resolution. when 12-bit resolution is required, pin 14 is connected to +5 v (pin 16). when 10-bit resolution is required, pin 14 is connected to bit 11 output pin 2. the conversion cycle then terminates, and the status flag resets after the bit 10 decision (t 10 + 40 ns in timing diagram of figure 10). short cycle pin connections and associated maximum 12-, 10-, and 8-bit conversion times are summarized in table 2 .
ad adc84/ad adc85 rev. b | page 8 of 12 input scaling the ad adc84/ad adc85 inputs should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the a/d converter. connect the input signal as shown in table 3. see figure 11 for circuit detail. figure 11. input scaling circuit table 2. short cycle connections connect short cycle pin 14 to pin connect clock rate control pin 17 to pin bits resolution (% fsr) ad adc84/ad adc85 conversiontime (s) status flag reset 16 15 12 0.024 10 (5) t 12 + 40 ns 2 16 10 0.100 8.5 (4.1) t 10 + 40 ns 4 28 8 0.390 6.8 (3.3) t 8 + 40 ns table 3. input s c aling c onne ctions input signal range output code connect pin 23 to pin connect pin 25 to for direct input connect input signal to pin input pin 30 connect pin 29 to pin 10 v cob or ctc 22 input signal 25 25 5 v cob or ctc 22 open 24 24 2.5 v cob or ctc 22 pin 22 24 24 0 v to +5 v csb 26 pin 22 24 24 0 v to +10 v csb 26 open 24 24 input voltage range and lsb values table 4. input voltages and code definition analog input voltage range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v code designation cob 1 or ctc 2 cob or ctc cob or ctc csb 3 csb one least significant bit (lsb) n 2 fsr n = 8 n = 10 n = 12 n 2 20v 78.13 mv 19.53 mv 4.88 mv n 2 10v 39.06 mv 9.77 mv 2.44 mv n 2 5v 19.53 mv 4.88 mv 1.22 mv n 2 10v 39.06 mv 9.77 mv 2.44 mv n 2 5v 19.53 mv 4.88 mv 1.22 mv transition values msb lsb 000 . . . 000 4 +full scale +10 v C3/2 lsb +5 v C3/2 lsb +2.5 C3/2 lsb +10 v C3/2 lsb +5 v C3/2 lsb 011 . . . 111 mid scale 0 0 0 +5 v +2.5 v 111 . . . 110 Cfull scale C10 v +1/2 lsb C5 v +1/2 lsb C2.5 v +1/2 lsb 0 v +1/2 lsb 0 v +1/2 lsb 1 cob = complementary offset binary. 2 ctc = complementary twos complement C obtained by using the complement of the most significant bit ( msb ). msb is available to pin 13. 3 csb = complementary straight binary. 4 voltages given are the nominal value for transition to the code specified.
ad adc84/ad adc85 rev. b | page 9 of 12 calibration external zero adj and gain adj potentiometers, connected as shown in figure 12 and figure 13, are used for device calibration. to prevent interaction of these two adjustments, zero is always adjusted first and then gain. zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and Cfs for bipolar input ranges). gain is adjusted with the analog input near the most positive end of the analog range. figure 12. analog and power connections for unipolar 0 to +10 v input range with buffer follower figure 13. analog and power connections for bipolar C10 v to +10 v input range with buffer follower 0 to +10 v range set analog input to +1 lsb = +0.0024v. adjust zero for digital output = 111111111110. zero is now calibrated. set analog input to +fsr C 2 lsb = +9.9952v. adjust gain for 000000000001 digital output code; full-scale (gain) is now calibrated. half- scale calibration check: set analog input to +5.0000 v; digital output code should be 011111111111. C10 v to +10 v range set analog input to C9.9951 v; adjust zero for 111111111110 digital output (complementary offset binary) code. set analog input to +9.9902 v; adjust gain for 000000000001 digital output (complementary offset binary) code. half-scale calibration check: set input to 0.0000v; digital output (complementary offset binary) code should be 011111111111. other ranges representative digital coding for 0 to +10 v and C10 v to +10 v ranges is given above. coding relationships and calibration points for 0 to +5 v, C2.5 v to +2.5 v, and C5 v to +5 v ranges can be found by halving the corresponding code equivalents listed for the 0 to +10 v and C10 v to +10 v ranges, respectively. zero and full-scale calibration can be accomplished to a precision of approximately ? lsb using the static adjustment procedure described above. by summing a small sine or triangular-wave voltage with the signal applied to the analog input, the output can be cycled through each of the calibration codes of interest to more accurately determine the center (or end points) of each discrete quantization level. grounding many data acquisition components have two or more ground pins which are not connected together within the device. these grounds are usually referred to as the logic power return, analog common (analog power return), and analog signal ground. these grounds must be tied together at one point, usually at the system power-supply ground. ideally, a single solid ground would be desirable. however, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the ground pin of the ad adc84/ ad adc85. separate ground returns should be provided to minimize the current flow in the path from sensitive points to the system ground point. in this way, supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. each of the ad adc84/ ad adc 85 supply terminals should be capacitively decoupled as close to the device as possible. a large value capacitor such as 1 f in parallel with a 0.1 f capacitor is usually sufficient. analog supplies are bypassed to the analog power return pin and the logic supply is bypassed to the logic power return pin.
ad adc84/ad adc85 rev. b | page 10 of 12 clock rate control alternate connections if adjustment of the clock rate is desired for faster conver- sion speeds, the clock rate control may be connected to an external multiturn trim potentiometer with a tcr of 100 ppm/c or less as shown in figure 14 and figure 15. if the potentiometer is connected to C15 v, conversion time can be increased as shown in figure 5. if these adjustments are used, delete the connections shown in table 2 for pin 17. see figure 2 for nonlinearity error versus conversion speed and figure 5 for the effect of the control voltage on clock speed. figure 14. 12-bit clock rate control optional fine adjust figure 15. 8-bit clock rate control optional fine adjust microprocessor interfacing the fast conversion times of the ad adc84/ad adc85 suggests several methods of interface to microprocessors. in systems where the adc is used for high sampling rates on a single signal which is to be digitally processed, cpu-controlled conversion may be inefficient due to the slow cycle times of most microprocessors. it is generally preferable to perform conversions independently, inserting the resultant digital data directly into memory. this can be done using direct memory access (dma), which is totally transparent to the cpu. interface to user-designed dma hardware is facilitated by the guaranteed data validity on the falling edge of the eoc signal. clearly, 12 bits of data must be broken up for interface to a 8-bit wide data bus. there are two possible formats: right-justified and left-justified. in a right-justified system, the least significant 8 bits occupy one byte and the four msbs reside in the low nibble of another byte. this format is useful when the data from the adc is being treated as a binary number between 0 and 4095. the left-justified format supplies the eight most- significant bits in one byte and the 4 lsbs in the high nibble of another byte. the data now represents the fractional binary number relating the analog signal to the full-scale voltage. an advantage to this organization is that the most-significant eight bits can be read by the processor as a coarse indication of the true signal value. the full 12-bit word can then be read only when all 12 bits are needed. this allows faster and more efficient control of a process. figure 16 shows a typical connection of 8085-type bus, using a left-justified data format for unipolar inputs. status polling is optional, and can be read simultaneously with the 4lsbs. if it is desired to right-justify the data, pins 1 through 12 of the adadc84/ad adc85 should be reversed, as well as the connections to the data bus high and low byte address signals. when dealing with bipolar inputs (5v, 10v ranges), using the msb directly yields a complementary offset binary-coded output. if complementary twos complement coding is desired, it can be produced be substituting msb (pin 13) for the msb. this facilitates the arithmetic operation which are subsequently performed on the adc output data. figure 16. ad adc84/ad adc85 C 8085a interface connections
ad adc84/ad adc85 rev. b | page 11 of 12 outline dimensions 0.120 (3.05) min 0.020 (0.51) 0.016 (0.41) 0.100 (2.54) bsc 0.060 (1.52) 0.040 (1.02) 0.910 (23.11) 0.890 (22.61) 0.012 (0.31) 0.009 (0.23) 1 16 17 32 pin 1 0.230 (5.84) max 1.640 (41.66) 1.584 (40.64) 0.005 (0.13) min all four corners 0.905 (22.99) 0.880 (22.35) 0.180 (4.57) min 0.055 (1.39) 0.045 (1.14) 0.080 (2.03) max all four corners controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design figure 17. 32-lead side brazed ceramic dip [sbdip/h] (dh-32f) esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model 1 operation voltage (v) linearity (%) temperature range gain tc (ppm/c) conversion time (s) adadc84-12 2 15 0.012 0c to +70c 30 10 adadc84z-12 2 12 0.012 0c to +70c 30 10 adadc85c-12 2 15 0.012 0c to +70c 25 10 adadc85-12 15 0.012 C25c to +85c 15 10 adadc85z-12 2 12 0.012 C25c to +85c 15 10 adadc85s-12 15 0.012 C55c to +125c 25 10 ADADC85SZ-12 12 0.012 C55c to +125c 25 10 adadc85s12/883b 15 0.012 C55c to +125c 25 10 adadc85sz12/883 12 0.012 C55c to +125c 25 10 1 for complete model number, suffixes must be added for z option (12 v operation), linearity. the following guide shows the p roper suffix order: ad adc(*)(**)-(***), where * = model number, ** = z version designator, and *** = linearity. typical part numbers: ad adc84-12, ad adc85sz-12. 2 last time buy.
ad adc84/ad adc85 rev. b | page 12 of 12 notes ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03262C0C11/03(b)

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